A communication system uses an error correcting code in order to ensure reliable communication through a channel. A low density parity check (LDPC) code exhibiting performance close to the Shannon limit is a representative error correcting code. The LDPC code has higher performance in comparison to a turbo code as a message size is greater, and does not show an error floor at relatively high SNR (Signal to Noise Ratio). The LDPC code may be expressed using a Tanner graph which shows a connection state according to edges between a bit node and a check node. A LDPC decoder operates by operating and updating information transferred along the edges between nodes on the Tanner graph.
Generally, the LDPC code has very great coding complexity, and thus leads to excessive use of a system storage and becomes a main restraint factor when implementing LDPC codes. In addition, when implementing LDPC codes, access conflict among memories storing bit nodes, check nodes, and their input/output values may cause serious problems. Therefore, an efficient decoder structure capable of solving these problems is needed.